Nvidia forces memory suppliers to adopt TSMC process for new chips
Nvidia requires Samsung, SK Hynix and Micron to use TSMC’s 3nm process for base dies in its custom high-bandwidth memory modules.
Key points
- Nvidia mandates TSMC 3nm base dies for all NVHBM suppliers to ensure design consistency and reduce validation overhead.
- The move marks the first collaboration between Samsung and TSMC on high-bandwidth memory production, shifting from a turnkey model.
- NVHBM architecture relocates the memory controller to the base die, promising higher bandwidth and lower power consumption than standard HBM4E.
Nvidia has instructed all three of its custom high-bandwidth memory suppliers to manufacture the base die using TSMC’s 3-nanometre process, according to a report by The Next Web citing Seoul Economic Daily. This directive applies to Samsung Electronics, SK Hynix and Micron, marking a significant shift in the supply chain for Nvidia’s NVHBM modules. The change aims to standardise production methods across different manufacturers, ensuring that the final chips perform consistently regardless of which supplier produced them. Previously, suppliers used their own processes for the logic layer, which complicated Nvidia’s validation efforts and created performance variances between batches.
Samsung Electronics agreed to this new arrangement after an internal review, despite traditionally using a turnkey approach where it manufactured both the base die and the memory dies above it. This marks the first time Samsung and TSMC have collaborated on making high-bandwidth memory, although the two companies worked together four years ago to align Samsung’s HBM with TSMC’s packaging processes. By adopting a common process, Nvidia avoids the need to validate each supplier’s chips separately, streamlining the integration of these critical components into its graphics processing units.
What we know
The NVHBM design, unveiled in August, moves the memory controller off the GPU and onto the base die, freeing up space on the graphics processor for additional computing circuits. This architectural change allows the physical layer that communicates with other chips to be 60 per cent smaller than in standard high-bandwidth memory. According to Seoul Economic Daily, this results in up to 30 per cent more bandwidth and 15 per cent less power consumption compared to standard HBM4E. Nvidia also requires the memory dies to be standardised on 1c, the sixth generation of DRAM technology, while the overall design follows the seventh-generation HBM4E standard.
Industry analysts note that TSMC’s 3nm process has a yield rate of more than 90 per cent, which is significantly higher than the approximately 60 per cent yield for Samsung Foundry’s comparable 2nm process, SF2. This reliability is crucial given the projected shortfall in high-bandwidth memory supply. UBS expects demand to reach 61.5 billion gigabits next year, a 91 per cent increase, while new shipments are forecast at only 54.6 billion gigabits, leaving a 10 per cent gap. TSMC is expanding capacity with two new 3nm lines at its Fab 18 in Tainan, with mass production starting in the first half of 2027 and 2028.
Defender's checklist
- Monitor supply chain announcements for changes in semiconductor manufacturing partners that could affect hardware availability.
- Review vendor documentation for performance specifications of new memory modules to understand potential efficiency gains.
- Assess internal infrastructure readiness for higher-bandwidth memory requirements as AI workloads continue to grow.
- Track industry yield rates and production timelines to anticipate potential bottlenecks in component supply.
The background in plain language
Organisations relying on high-performance computing need to understand how memory architecture impacts system efficiency. When memory controllers move closer to the processing units, data transfer speeds increase while power consumption drops. Supply chain standardisation reduces the risk of compatibility issues, ensuring that components from different manufacturers work seamlessly together. Teams usually evaluate vendor strategies for quality control and yield rates to predict product availability. Check whether your hardware vendors are aligning with industry-wide manufacturing standards to minimise integration delays.
What to do and how to stay safe: Nvidia
- Review your organisation’s hardware procurement strategy to account for potential supply constraints in high-bandwidth memory.
- Evaluate the performance benefits of next-generation memory architectures for your specific computing workloads.
- Monitor vendor communications regarding manufacturing process changes that could impact product release schedules.
- Consider the long-term implications of supply chain consolidation on hardware diversity and resilience.
General security guidance from the TechWire Beat newsroom. It is not confirmed advice from the organisations named in this story.
Frequently asked questions
Why is Nvidia requiring suppliers to use TSMC’s 3nm process?
Nvidia wants consistency across its NVHBM suppliers to ensure uniform performance and avoid validating each supplier’s chips separately.
Which companies are affected by this change?
Samsung Electronics, SK Hynix and Micron, all three of Nvidia’s NVHBM suppliers, must use TSMC’s 3nm process for the base die.
What are the performance benefits of NVHBM?
NVHBM offers up to 30 per cent more bandwidth and 15 per cent less power consumption than standard HBM4E by moving the memory controller to the base die.
